Mainframe computer systems such as the IBM eServer z900® system, offered by International Business Machines Corporation, Armonk, N.Y., comprise a plurality of processors. (IBM® is a registered trademark of International Business Machines, Armonk, N.Y., U.S.A. Other names used herein may be registered trademarks or product names of International Business Machines or other companies.) These large systems are capable of processing a large number of tasks in a short period of time. It is frequently desirable to divide this host processing power into separate partitions of “virtual machines” that can be operated by different users. The division is accomplished by the use of host control program software. Virtual machines with multi-level guests are described in the patent U.S. Pat. No. 5,317,705 A. Each of the virtual machines can accept a “guest” operating system that may be different from the host operating system. The guest virtual machines may in turn be divided into additional virtual machines for performance of certain tasks.
A guest may also use dynamic address translation (DAT). A guest virtual address 10 is first translated to a guest real address 12, using guest translation tables, see FIG. 1. The guest real address 12 is converted to a host virtual address by adding to it the host virtual address (step 14) at which the guest storage begins (host origin) in the host address space. The host address is then translated to the host real address 16 by using the host translation tables.
Address translation is usually performed by dedicated hardware circuitries consisting of a translation engine 26 and the translation lookaside buffer (TLB) 28 in a central processing unit (CPU) 20, as shown in FIG. 2. The translation engine 26 executes the translation process, i.e. fetches memory data that contain the translation tables stored in main memory 30 via a first level high speed cache 24 and a second level medium speed cache 22. The combined region- and segment-table entry (CRSTE) portion of TLB 28 contains the page-table origin (PTO), which is the translation results of all region- and segment-table entries. The page-table entry (PTE) portion of TLB 28 stores the recently used page table entries. A translation table entry is usually 8 bytes wide. Fetching this entry usually transfers a so called cache line from main memory 30 to the first and second level caches, which contains the 8 byte translation table data. The translation engine 26 is also known as picocode engine. Such a picocode engine is described by T. J. Slegel, E. Pfeffer and J. A. Magee in “The IBM eServer z990 microprocessor”, IBM J. Res. & Dev., vol. 48, no. 3/4, May/July 2004 which is incorporated for disclosure by its entirety.
The principle of the translation process is shown in FIG. 3. The IBM ESAME architecture describes the address translation process in detail; it uses up to five different translation tables, i.e. region, segment (ST) 42, and page tables (PT) 44. The effective address-space-control-element (ASCE) 40 designates the translation table to be used. For simplicity reasons the segment table 42 was chosen, which allows to translate virtual addresses up to a width of 31 bits. The ASCE 40 with table origin (TO) and designation type (DT) contains the segment-table origin (STO); the segment index portion (SX) of the virtual address 50 is added to select an entry in the segment table 42. The segment table entry STE contains the page table origin (PTO) and the page index portion (PX) of the virtual address 50 is added to select an entry in page-table, which contains the page-frame real address (PFRA). When this address is concatenated with the byte index field BX of the virtual address, a real address 46 is obtained.
The TLB captures the results of DAT and provides a shortcut for future translations. It has a limited capacity, so only a certain number of recent translations are maintained (e.g. 4096). The Translation Engine tests whether or not a translation from virtual to real is available in TLB. If available, it is used and DAT is bypassed. The background of the invention is described by T. J. Slegel, E. Pfeffer and J. A. Magee in “The IBM eServer z990 microprocessor”, IBM J. Res. & Dev., vol. 48, no. 3/4, May/July 2004, particularly on pp. 295-309.
Prior art TLB can store intermediate translation results of a certain guest level, as disclosed in U.S. Pat. No. 6,418,522 B1. The principle is depicted in FIG. 4. IBM mainframe ESAME requires five fetches to translate a 64-bit address and usually just the page index of the virtual address changes. Hence the change affects only the lowest and last one used table, for which the start address of it will be saved, i.e. the page table origin (PTO) and can be used again, if this page table is required. Thus, all accesses to the higher translation tables, as e.g. segment, region tables are bypassed (bypass 70 bypassing fetching of segment table entry STE from the second level cache in 64) and page table entry PTE is fetched from the first level cache L1 in 66 and a Real Address is obtained in 68. For this purpose the TLB is arranged in two portions as mentioned above (see FIG. 2). The combined region- and segment-table entry (CRSTE) portion contains the translation results of all region- and segment-table entries, which is the page-table origin. The page-table entry (PTE) portion of the TLB stores the recently used page table entries PTE. Thus, following a TLB lookup 60, a TLB hit 62 in the CRSTE portion bypasses (bypass 70) accesses to all region- and segment tables.
As shown in FIG. 4 bypassing access to the region and segment tables will save one table fetch (fetch from second level cache in 64), if a translation starts with an access to the segment table; more table fetches will be saved if region tables are in use. As shown in FIG. 5, which is discussed below in detail, there are at least five table fetches necessary to translate a guest virtual address. These table-fetches lead to considerable CPU performance loss.